Bellmac 32

The Bellmac 32 is a microprocessor developed by Bell Labs' processor division in 1980, implemented using CMOS technology and was the first microprocessor that could move 32 bits in one clock cycle. The microprocessor contains 150,000 transistors and improved on the speed of CMOS design by using "domino circuits". It was designed with the C programming language in mind. After its creation, an improved version was produced called the Bellmac 32A, then cancelled along with its successor, the "Hobbit" C-language Reduced Instruction Set Processor (CRISP).

History

The Bellmac 32 processor was developed by AT&T engineers in three different Bell Labs locations: Indian Hill, Homdel and Murray Hill.[1]

As the designers did not have automation tools, every chip designer had to use colored pencils for the completion of the initial design.[1] Later, Steve Law developed a computer program that aided in the digitization of the initial designs.

The development of the Bellmac 32 produced a novel circuit design technique called domino logic, deemed a breakthrough for the production of the microprocessor. Tests performed during manufacture indicated that a clock frequency even higher than the 4 MHz target speed was possible. Implementing the control logic, however, proved unexpectedly complicated. These complications limited the final speed, when the entire chip was finished and tested, to 2 MHz.[1] The team considered it as progress, but not as successful, as it could not meet the initial AT&T design goals.

Followup design meetings resulted in the Bellmac 32A project, as a second generation of the Bellmac microprocessor. The project once again selected CMOS technology and fixed the target clock frequency at 6.2 MHz. Adjustments to maximize the size of transistors and resistors and minimizing interconnections were fundamental in meeting the specifications. The engineers placed a 20-foot-by-20-foot engineering drawing of the chip layout on the floor of a large room.[2] Testing of chips produced from the completed circuit exceeded the design speed, and reached clock frequencies of 7, 8, and even 9 MHz.[1]

After the breakup of AT&T, Bell Labs became a component of Western Electric. With this change, the Bellmac 32 was renamed to WE 32000. Updated versions of the chip included the WE 32100 and WE 32200 processors.

Architecture

The Bellmac 32 has a pipelined architecture with an instruction fetch unit that serves to control access to main memory, and an execution unit which serves to monitor the process and manipulate data.

The instruction queue is filled with the instructions fetched from the memory. The address arithmetic unit serves for address calculations.

Bellmac 32 hardware is able to store all instructions, data and register contents associated with a process during a context switch.

Registers

Bellmac 32 has sixteen 32-bit registers. Three of these (ISP, PCBP, PSW) are privileged, used to support the operating system and can be written only when the microprocessor is in kernel mode. There are three other registers (SP, AP, FP) that are used by some instructions as stack pointers. Execution level, set in the Processor Status Word, can be one of four states: Kernel, Executive, Supervisor, User.[3] There are an additional sixteen registers in the WE 32200.[4]

WE 32100 registers
31 ... 23 ... 15 ... 07 ... 00 (bit position)
General registers
R0 Register 0
R1 Register 1
R2 Register 2
R3 Register 3
R4 Register 4
R5 Register 5
R6 Register 6
R7 Register 7
R8 Register 8
R9 / FP Frame Ptr
R10 / AP Argument Ptr
R11 / PSW (See below) Processor Status Word
R12 / SP Stack Ptr
R13 / PCBP Process Control Bock Ptr
R14 / ISP Interrupt Stack Ptr
R15 / PC Program Counter

Processor status word

The Process Status Word is part of the register file and is aliased as R11.

Unused CFD QIE CD OE N Z V C TE IPL CM PM R I ISC TM ET
31 25 24 23 22 21 20 19 18 17 16 12 10 8 7 6 2 1
Bits Meaning
31:26 Unused
25 Cache Flush Disable
24 Quick-Interrupt Enable
23 Cache Disable
22 Enable Overflow Trap
21 Negative
20 Zero
19 Overflow
18 Carry
17 Trace Enable
16:13 Interrupt Priority Level
12:11 Current Execution Level
10:9 Previous Execution Level
8:7 Register-Initial Context
6:3 Internal State Code
2 Trace Mask
1:0 Exception Type

Instructions

This microprocessor has 169 instructions, which are optimized for executing programs written in the C programming language. Accordingly, the format of character strings is adapted to C language specifications, for example.

The instructions may have up to three operands. The processor has no floating-point or decimal arithmetic instructions, which were later provided by coprocessors WE 32106 and WE 32206.

Memory

The Bellmac 32 implements multiple types of memory addressing, such as linear, immediate 8, 16 or 32 bits, registration, register indirect, short shift, absolute and indirect displacement of 8, 16 or 32 bits.

Usage

The WE 32x00 processors were used in the AT&T Computer Systems' 3B series computers.

Supporting chips

AT&T had a lineup of WE 32x00 supporting chips and peripherals,[4] including:

  • WE 32101 / 32201 Memory Management Unit
  • WE 32102 Clock (10, 14, 18, or 24 MHz)
  • WE 32103 DRAM Controller
  • WE 32104 / 32204 DMA Controller
  • WE 32106 / 32206 Math Acceleration Unit
  • WE 321SB VMEbus Single Board Computer
  • WE 321EB Evaluation Board

References
  1. Dr. Sung Mo (Steve) Kang (13 January 2015). "First-Hand:The AT&T BELLMAC-32 Microprocessor Development". Engineering and Technology History Wiki.
  2. http://greg.org/archive/2011/12/09/on_the_bellmac-32_and_perhaps_the_worlds_largest_plotter_pen_drawing.html
  3. "WE 32100 Microprocessor Information Manual" (PDF). AT&T. January 1985.
  4. "AT&T WE 32-Bit Microprocessors and Peripherals" (PDF). AT&T. August 1987.
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